1. Field of the Invention
The present invention relates to a test structure and its application for inspecting an electrical device; and more particularly, relates to a test structure and method for detecting sub-threshold leakage defect in an electrical device.
2. Description of the Prior Art
The sub-threshold leakage is a current that flows from the drain to source of a metal-oxide-semiconductor-field-effect-transistor (MOSFET) when the transistor is supposed to be off. When the transistor is turned off or the voltage supplied to the gate of the transistor is lower than its threshold voltage, ideally the conduction between the drain and source should be smaller than a predefined acceptable value, wherein this value is mainly dependent upon the functionality of the device to which the concerned transistor belongs. For example, the threshold value for a device in a microprocessor could be higher than that in a cell phone circuit. In reality, the Boltzmann distribution of electron energies allows some of the more energetic electrons at the source to enter the channel and flow to the drain, resulting in a sub-threshold current. Other causes such as a changed threshold voltage value of a device transistor due to wrongly implanted dopant type or non-uniform dopant distribution would also lead to the occurrence of sub-threshold leakage.
Referring to FIG. 1A which is a schematic illustration of an NMOS transistor 100A without the sub-threshold leakage. As shown, NMOS transistor 100A comprises a gate 101A, an n-type doped region 102A (source) and an n-type doped region 103A (drain) formed on a p-type well 104A and a p-type substrate 105A. A gate voltage Vg is supplied to gate 101A, a drain voltage Vd is applied to drain 103A, and source 102A is grounded. An equivalent circuitry of NMOS transistor 100A is shown as 106A with a gate G, a source S and a drain D. As NMOS transistor 100A does not have sub-threshold leakage, when it is turned off, Vg is equal to zero and there is no current flowing through the channel between source 102A and drain 103A i.e. the drain-to-source current at zero gate voltage, which is denoted as I_off, is equal to zero or less than an acceptable value.
Referring to FIG. 1B, which is a schematic illustration of an NMOS transistor 100B with sub-threshold leakage. As shown, NMOS transistor 100B comprises a gate 101B, an n-type doped region 102B (source) and an n-type doped region 103B (drain) formed on a p-type well 104B and a p-type substrate 105B. A gate voltage Vg is supplied to gate 101B, a drain voltage Vd is applied to drain 103B, and source 102B is grounded. An equivalent circuitry of NMOS transistor 100B is shown as 106B with a gate G, a source S and a drain D. As NMOS transistor 100B has sub-threshold leakage, when it is turned off, Vg again is equal zero but I_off is at this time not equal to zero or larger than an acceptable value.
The amount of sub-threshold conduction is set by the threshold voltage of the concerned transistor which sits between ground and the gate voltage (Vg), and so has to be reduced along with the supply voltage. That reduction means less gate voltage swing below threshold to turn the device off, and as sub-threshold conduction varies exponentially with gate voltage, it becomes more and more significant as MOSFETs shrink in size.
Charged particle beam systems such as electron beam inspection (EBI) systems are increasingly utilized in advanced integrated circuit chip manufacturing. The systems have high resolution that can be used to detect tiny physical defects that beyond the capability of optical defect inspection systems. Another advantage of the EBI system is that it can detect, through observation of a voltage contrast (VC) image, defects of electrical circuitry such as open circuit, short circuit or leakage on or underneath the wafer surface. This is based on the fact that semiconductor devices of different configurations give rise to different VC. For example, referring to part (1) of FIG. 2A which illustrates a cross-section of a semiconductor structure 20A. As shown, semiconductor structure 20A comprises an n-type doped region 21A formed in a p-type doped material 22A. As would be understood by those skilled in the art, semiconductor structure 20A may be seen as a diode 23A with a cathode 231A on top of an anode 232A, and with anode 232A being equivalent to being grounded due to its electrical connection to material 22A assuming material 22A has a large enough capacitance. Consequently, when semiconductor structure 20A or a plug connected to it is being scanned on the surface by a positive charging-inducing charged particle beam, diode 23A is inversely biased and positive charges will accumulate on the surface of semiconductor structure 20A or the surface of the plug connected thereto. This will hinder the secondary electrons from the surface of semiconductor structure 20A or its plug from reaching the detector, resulting in a dark voltage contrast (DVC) in the obtained charged particle microscopic image.
Semiconductor structure 20A may be used to form an n-type metal-oxide-semiconductor (NMOS) device 200A as illustrated in part (2) of FIG. 2A. As shown, NMOS device 200A comprises a p-type doped substrate 210A, a p-type doped well 220A, a p-type doped region 230A, heavily n-type doped (N+) source and drain region (S/D) 240A, a very thin layer of gate dielectric 250A, a conducting gate electrode 260A and sidewall spacers 270A. It is noted that well 220A may be dispensed with such that doped region 240A is in direct contact with substrate 210A. Or, in some cases substrate 210A may be so referred to as including well 220A when both of them are of the same dopant type.
Referring to part (1) of FIG. 2B which illustrates a cross-section of a semiconductor structure 20B. As shown, semiconductor structure 20B comprises a p-type doped region 21B formed in an n-type doped material 22B. As would be understood by those skilled in the art, semiconductor structure 20B may be seen as a diode 23B with an anode 231B on top of a cathode 232B, and with cathode 232B being equivalent to being grounded due to its electrical connection to material 22B assuming material 22B has a large enough capacitance. Consequently, when semiconductor structure 20B or a plug connected to it is being scanned on the surface by a positive charging-inducing charged particle beam, diode 23B is forwardly biased. Therefore, electrons from n-type doped material 22B will reach the surface of semiconductor structure 20B or the surface of its plug and positive charges will not accumulate on the surface of semiconductor structure 20B or the surface of its plug but will be drained to ground (material 22B). This will allow more secondary electrons from the surface of semiconductor structure 20B or its plug to reach the detector, resulting in a bright voltage contrast (BVC) in the obtained charged particle microscopic image.
Semiconductor structure 20B may be used to form a p-type metal-oxide-semiconductor (PMOS) device 200B as illustrated in part (2) of FIG. 2B. As shown, PMOS device 200B comprises a p-type doped substrate 210B, a n-type doped well 220B, a n-type doped region 230B, heavily p-type doped (P+) source and drain region (S/D) 240B, a very thin layer of gate dielectric 250B, a conducting gate electrode 260B and sidewall spacers 270B. It is noted that well 220B may be dispensed with such that doped region 240B is in direct contact with substrate 210B. Or, in some cases substrate 210B may be so referred to as including well 220B when both of them are of the same dopant type.
Referring to part (1) of FIG. 2C which illustrates a cross-section of a semiconductor structure 20C. As shown, semiconductor structure 20C comprises a p-type doped region 21C formed in a p-type doped material 22C. As would be understood by those skilled in the art, semiconductor structure 20C may be seen as a resistor 23C which is equivalent to being grounded due to its electrical connection to material 22C assuming material 22C has a large enough capacitance. Consequently, when semiconductor structure 20C or a plug connected to it is being scanned on the surface by a positive charging-inducing charged particle beam, again as in the case in FIG. 2B the positive charges will not accumulate on the surface of semiconductor structure 20C or the surface of its plug but will be drained to ground (material 22C). This will facilitate generation of the secondary electrons from the surface of semiconductor structure 20C or its plug, resulting in a bright voltage contrast (BVC) in the obtained charged particle microscopic image.
Semiconductor structure 20C may be used to form a p-type metal-oxide-semiconductor (PMOS) device 200C as illustrated in part (2) of FIG. 2C. As shown, PMOS device 200C comprises a p-type doped substrate 210C, a p-type doped well 220C, a p-type doped (P+) region 230C, heavily p-type doped (P+) source and drain (S/D) 240C, a very thin layer of gate dielectric 250C, a conducting gate electrode 260C and sidewall spacers 270C. It is noted that well 220C may be dispensed with such that doped region 240C is in direct contact with substrate 210C. Or, in some cases substrate 210C may be so referred to as including well 220C when both of them are of the same dopant type.
As mentioned earlier, charged particle beam inspection can be used to examine presence of varies defects in a fabricated MOSFET by observing the voltage contrast (VC) image thereof. However, the sub-threshold leakage within a static random access memory (SRAM) array is not easy to be inspected by charged particle beam inspection such as EBI, because the scanning charged particle beam gives rise to an equal surface charging (thus surface potential) to plugs with a similar underneath connected electrical devices. In other words, there would be no bias voltage between the source and drain of a MOSFET to which the scanned plugs are connected. As a result, even the sub-threshold leakage exceeds the acceptable conduction current value at designated drain voltage Vd, both the normal and defective source/drain plugs look the same in the obtained charged particle voltage contrast image. For example, they may both display a dark voltage contrast (DVC). This makes it difficult to identify the defective MOSFET which has sub-threshold leakages.
Accordingly, test structures and application method thereof are needed to facilitate charged particle beam-based inspection of the sub-threshold leakage.